Although this post is specific to the semiconductor industry, I dare say the subject of transformation is equally as interesting in other industries.
What does a semiconductor company look like today? If we go back 25 years or more, the answer was relatively easy – the design and manufacture of custom integrated circuits for sale in broad multi-market applications. There were design houses (full custom) as such, but the majority of design/development was in captured manufacturers such as Fairchild, National semi, TI, Intel, IMB, et al.
Then we saw the onset of fabless semiconductor companies during the early 80′s. While these fabless companies performed IC design, they depended on partnerships with an IDM (integrated device manufacturer) to get their product into production. During the later 80′s we saw the introduction of semi-custom IC design, manifest in the form of digital gate arrays and standard cells. This elevated IC design flows to exclude actual transistor design – the flow required only simple knowledge of basic functions (NAND, NOR, Flip-Flop etc.). This allowed a new wave of fabless semicon companies to be born. By the end of the 80′s, the semiconductor foundry business model had been created which further stimulated the growth of fabless semiconductor companies. The escalation in Fabless companies increased the size of the playing field for EDA suppliers and also stimulated the IP business model. Standard cells, CPUs, MPUs, memory, IO and ultimately application specific IP brokering became the name of the game.
It was initially difficult for IP suppliers to work directly with IDM/Fabless companies because of their dependence on specific manufacturing processes – IP companies could not cover all processes and all foundries. Although CMOS became the focal process point, not all CMOS processes were equal! The IP players gravitated toward the foundries as natural partners – IP proven in a given process and ultimately sold as a cost adder to a wafer.
The business models for semiconductor companies continued to evolve during the 90′s – but the capital requirements for owning and running fabrication lines (fabs) were starting to become prohibitive. Once we hit a $1B capital outlay for a fab, even the IDMs started to increase the outsourced manufacturing – especially in the leading-edge nodes. So now we have IDMs shifting to the fab-lite business model (no new investment in fabs), and the fabless semiconductor companies depending more on the foundry/IP partnership.
Let’s not forget the “glue” in all of this – the EDA companies. The tools that enabled IP companies to deliver libraries to foundries (and design house services) had to try and maintain par with the rapid advancement of technology nodes. Although one could say that EDA tools had been somewhat abstract up until the early 90′s, the need for tools to be tightly coupled with processes, as well as design flows, was now crucial.
As we entered the new millennium, the fabless semiconductor business model was undergoing another transformation. Integration was reaching such high levels, that the emphasis shifted to system design rather than chip design – enter the System-on-Chip (SoC) era. Although an embedded core plus memory and IO could arguably be called a system-on-chip, the acronym was more suitable to an SoC that had a specific application and would likely include some standards protocol. Both IDM and fabless companies would find it progressively more difficult and costly to develop all of the required IP in-house, further promoting the demand of readily available (proven) IP blocks from suppliers and/or foundries. The need for EDA tools to not only be more tightly linked to a process, but also a more tightly linked modeling level for increasing more complex IP elements, continued to mount.
Most recently, we have seen many fabless companies now become fabless and chipless – meaning they no longer retain circuit, layout, test, product or quality engineers. Their requirements have moved to architects, software and system engineers. Although they may sell an SoC in which their product is embedded, we can hardly call them a semiconductor company. Likewise, the foundries had formed partnerships (mostly through direct investment) with chip design houses, to create the channel for fabless/chipless companies (and indeed many OEMs) to take receipt of finished goods for sale in their target markets.
So who now are the semiconductor companies? I think we can all agree that the foundries are indeed semiconductor companies, but what about the changing nature of deisgn flows and traditional “back-end” activities? I believe there is also a case to be made that EDA players will continue to evolve toward a true semiconductor company where process, design, manufacturability and test will be their “backyard”.
The current economic and industrial downturn will see many companies fall by the wayside, be they fabless, chipless, IP or foundry. This will create a new wave of consolidation in both IP/technology and products. All IP has a “shelf-life” therefore it is incumbent on acquirers/buyers to ensure they are able to quickly make these levels of consolidation productive. We must remember that “all that glitters is not gold”.
I read an article in EDAcafe last week – it was an interview with Jack Harding, CEO of eSilicon. His comments are insightful and I believe accurate. Here is the link.
Just a final thought that probably will form the basis for another posting. I have been using the term “near product” more and more in the last two years. The cost of product development for an SoC has gone vertical! While the actual cost of design and manufacturing of SoCs in bleeding-edge processes is enormous, the additional cost of software development, protocol, standards compliance and delivery of a platform (full eBOM) that a customer can quickly turn into an end product, is equally enormous. The Soc and platform are reaching a “near product” level, where customers are offered fastest path to revenue – how do we ensure customers pay for this “near product” rather than just an SoC?
It does not take a big stretch of imagination to think of TSMC as “The Semiconductor Company.” They just farm out Product Development, Marketing and Sales to a bunch of subordinate vendors.
True, but historically we have thought of the foundries as just that – a manufacturing service. In recent years they have been drawn into a more complete semiconductor company. They do not architect, design or support required software for ICs, nor do they sell the product or provide applications support – this is the role of the fabless/chipless company, and the product groups within the larger players who are moving more toward an outsourcing model to ensure access to leading-edge processes.
Hi Mike,
I chanced upon your blog thru Simon Dickinson [my ex-colleague].
I am taking alot away from your insightful review of the semicon industry as is yesterday, today and forecasting tomorrow. THANK YOU!
I also realised that you were with CHRT [me with them from 1999-2007] before in the very early years! 1990-2!
If you have no objection i will like to invite you into my linkedIn connection.
Sincerely,
Vince
Hi Vince, I will be happy to link up in LinkedIn. Simon was with me at Anadigm (he joined us from Chartered!). Indeed, semiconductor world is small (and unfortunately getting smaller!!). Rgds/Mike
Mike,
Insightful article. I’ve been having the same discussion with a group of fellow chip design engineers. We have decided that it’s time for us to move into system level design or move over to applications and product engineering. Our quess is 50% of design will be gone from the US in 5 years and the major that will be left will be systems integration and design.
Woody,
Your input is much appreciated. You raise another interesting point with respect to the role of a chip designer. If we are discussing what a semiconductor company looks like today, then indeed we should also discuss the definition of a chip designer. For more exotic RF/linear/power processes and some challenging analog circuits I believe we still have the need for highly skilled transistor level design and custom layout engineers in design houses. There is also a need for transistor level designers inside the large scale memory, CPU and IP supplier companies. But the proliferation of IP blocks offered/brokered through EDA and/or foundries (as well directly!), has changed the nature of what chip design means. By elevating the SoC design role to one of architecture, system partitioning and implementation (where the implementation already represents a service provided by eSilicon, Faraday, Open-Silicon, eASIC, Key ASIC et al), we are asking the new breed of “chip designers” to be architects who can partition a system into the most efficient, high performance, low power structures possible, that are becoming more application specific. Developing a system level product for video processing requires knowledge of video streams, conversion rates, compression algorithms, standards, pixel correction etc., versus the silicon angle of ADC, DAC, DSP, CPU/MPU, RAM/ROM, I/O etc.
It would be interesting to get the views of both seasoned transistor level designers (typically with 20+ years of experience) and the newer breed of designers who are faced with the system level challenges (typically 5+ years of experience).